This application is related to my copending application U.S. patent application Ser. No. 754,607, filed Nov. 20, 1996 which is incorporated herein by reference. In that application, an improved p-channel IGBT device is described which is fully compatible with a generic process for making complementary pairs of MOS devices as well as IGBT devices. In this application I will describe a modification of that generic process to form an improved p-channel MOS device.
In a typical high voltage BiCMOS technology the n-channel high voltage MOS transistors are self-aligned or double diffused (DMOS). The complementary device, the p-channel device, is frequently not self-aligned or double diffused to keep the process complexity, and the cost, down. This results in less than optimum performance for the p-channel devices, e.g. higher on-resistance, and wider variation in manufacturing. In a non-self-aligned process greater margins are typically required for feature alignment and the overall device size is typically greater resulting in a decrease in device packing density and a proportional increase in cost.
As pointed out in my earlier application, device design in BiCMOS fabrication is heavily dependent on processing compatibility so a design improvement that appears advantageous for one type of device is only effective if it can be made within the constraints of the overall IC process. Thus, although it is easy to design a p-MOS device with a self-aligned gate, a way to do so within the constraints of the typical BiCMOS technology has not been available in the prior art.